1. Field of the Invention
The present invention provides a delay-locked loop device capable of anti-false-locking and related methods, and more particularly, a delay-locked loop device capable of decreasing the number of shift registers needed.
2. Description of the Prior Art
Digital integrated circuits have been highly developed. Personal computers, mobile phones, digital watches, and calculators, for example, are applications of digital integrated circuits. With high-speed, microminiaturized, and multi-function developments, a complex digital integrated circuit often includes a plurality of units. The units delay a reference timer with different degrees, so a delay-locked loop (DLL) device is need for maintaining synchronization of the digital integrated circuit. In order to improve effects of stuck lock, harmonic lock, small lock range and asymmetric duty cycle, the prior art provides a delay-locked loop device capable of anti-false-locking. Please refer to FIG. 1, which illustrates a schematic diagram of a prior art DLL device 100 capable of anti-false-locking. The DLL device 100 includes a phase detector 102, a charge pump 104, a loop filter 10, a voltage control delay circuit 108, a reference-phase generator 110, and a lock detector 116. The voltage control delay circuit 108 includes a plurality of delay units 112 for outputting a delayed phase Fde from the last delay unit 112 to the phase detector 102. The DLL device 100 forms a lock loop 114 according to a lock indication signal SpI provided by the lock detector 116, including an under signal Su, a right signal Sr, and an over signal So.
As to a configuration of the lock detector 116 in FIG. 1, please refer to FIG. 2. In FIG. 2, the lock detector 116 includes a frequency divider 118, a first shift register set 120, a second shift register set 122, and a logic module 124. The first shift register set 120 includes N units of D flip-flops 126, while the second shift register set 122 includes M units of D flip-flops 128. The frequency divider 118 outputs a first divided phase Fref_2 and a second divided phase Fref_2B according to rising edges of a reference phase Fref provided by the reference-phase generator 110. Frequencies of the first and second divided phases Fref_2 and Fref_2B are half the frequency of the reference phase Fref, and the second divided phase Fref_2B is the inverse of the first divided phase Fref_2. The DLL device 100 is free from the problem of duty-cycle asymmetry by using the frequency divider 118. In FIG. 2, the first shift register set 120 outputs the comparison signal QC1˜QCN+1 to the second shift register set 122 according to the first divided phase Fref_2 and the signals CK1˜CK(N+1) outputted from the delay units 112 of the voltage control delay circuit 108. Each D flip-flop 128 of the second shift register set 122 corresponds to each D flip-flop 126 of the first shift register set 120 for sampling the comparison signals QC1˜QCN+1 with the second divided phase Fref_2B, and outputting a sequence of comparison signals L1˜L(M+1) to the logic module 124. Then, the logic module 124 can output the lock indication signal SpI according to the comparison signals L1˜L(M+1).
Therefore, the DLL device 100 can prevent occurrences of false lock, stuck lock, harmonic lock, a small lock range and an asymmetric duty cycle. And, by increasing the D flip-flops 126, 128 in the first shift register set 120 and the second shift register set 122, the DLL device 100 can further increase the lock range and accuracy. However, the more D flip-flops 126 and 128 there are, the larger the DLL device 100 becomes, and the higher the production cost will be. Moreover, the DLL device 100 may cause a false lock because of inverse phases of output signals of the delay unit 112.
For example, please refer to FIG. 3, which illustrates a schematic diagram of a voltage control delay circuit having five stages of delay units 302 in a prior art DLL device. In FIG. 3, signals CK1˜CK5 respectively represent phases outputted from each delay unit 302, and signals CK1B˜CK5B represent inverse phases of the signals CK1˜CK5. Ideally, a reference phase Fref is delayed by each delay unit 302, and becomes the signals CK1˜CK5 outputting to a first shift register set. Also, an inverse phase FrefB of the reference phase Fref is delayed by each delay unit 302, and becomes the signals CK1B, CK2B, CK3B, CK4B, and CK5B. Please refer to FIG. 4 and FIG. 5. FIG. 4 illustrates a schematic diagram of signals of a false lock, and FIG. 5 illustrates a schematic diagram of phases corresponding to the signals in FIG. 4. Suppose that a required delay amount is one cycle, which means that an expected phase difference, between the signal CK5 outputted from the last delay unit 302 and the reference phase Fref, is 360°. However, comparing the phases, the phase difference between the reference phase Fref and the phase FrefB is 180°, so that if a phase difference between the signal CK5 and the reference phase Fref is 180°, then a phase difference between the inverse signal CK5B and the reference phase Fref is just 360°. Therefore, in FIG. 5, the first shift register set will output the comparison signals QC1–QC5 according to the signals CK2, CK4, CK1B, CK3B, and CK5B. In this situation, the phase difference between the locked phase and the reference phase Fref is only 180°, and a false lock occurs.
Therefore, the prior art DLL device suffers a false lock owing to inverse phases of signals outputted from the delay units of the voltage control delay circuit.